Management of Programming Mode Transitions to Accommodate a Constant Size of Data Transfer between a Host System and a Memory Sub-System

ABSTRACT

A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

RELATED APPLICATIONS

The present application is a continuation application of U.S. patent application Ser. No. 17/685,250 filed Mar. 2, 2022 and issued as U.S. Pat. No. 11,782,841 on Oct. 10, 2023, which is a continuation application of U.S. patent application Ser. No. 16/883,826 filed May 26, 2020 and issued as U.S. Pat. No. 11,294,820 on Apr. 5, 2022, which claims priority to Prov. U.S. Pat. App. Ser. No. 62/868,060 filed Jun. 28, 2019, the entire disclosures of which applications are hereby incorporated herein by reference.

TECHNICAL FIELD

At least some embodiments disclosed herein relate to memory systems in general, and more particularly, but not limited to management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system.

BACKGROUND

A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

FIG. 1 illustrates an example computing system that includes a memory sub-system in accordance with some embodiments of the present disclosure.

FIG. 2 shows a data transfer manager configured to control timing of data transfer between a host system and a memory sub-system.

FIG. 3 shows an example of a memory sub-system having timed data transfer.

FIG. 4 illustrates an example of data structures configured to support data transfer between a host system and a memory sub-system.

FIG. 5 shows a method of timed data transfer.

FIG. 6 illustrates of sizes of data to be programmed in atomic programming operations responsive to transitions of programming modes.

FIG. 7 shows a method to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system.

FIG. 8 is a block diagram of an example computer system in which embodiments of the present disclosure can operate.

DETAILED DESCRIPTION

At least some aspects of the present disclosure are directed to data transfer between a host system and a memory sub-system. For example, the data transfer is timed/scheduled to reduce the buffer memory requirement in the memory sub-system and thus reduce the requirement for a power-fail hold-up circuit in the memory sub-system. For example, transitions among atomic programming modes are managed to accommodate a constant size of data transfer between a host system and a memory sub-system. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1 . In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

Traditionally, caching based architectures are used in a memory sub-system to isolate the host system from the memory sub-system. When a write command is received in the memory sub-system from the host system, data is transferred from the host system to the cache in the memory sub-system. When the write workload exceeds the bandwidth of the media of the memory sub-system to commit, store, or program the data into the media, throttling of the input/output activities in the host system occurs due to the lack of available space in the cache buffer. While such architectures can provide a low latency write using cached data, it has disadvantages when the write workload exceeds the bandwidth of the media of the memory sub-system. For example, the number of outstanding commands that can be issued to the memory sub-system is limited by the size of the cache buffer memory in the memory sub-system. An increased size of the cache buffer memory increases the requirement for the energy storage capability of the power-fail back-up circuitry. Further, when two or more commands are mapped to the same media unit that can execute only one command at a time, a command collision occurs. The collision can lead to both higher buffer memory consumption and higher lifetime of data being stored in the buffer memory. This can result in increased system costs, in terms of increased size requirements for the cache buffer memory and increased energy storage capability of the power-fail hold-up circuitry. Further, a first write stream may block a second write stream by buffering data in the cache buffer memory and leaving no buffer space for the second write stream such that even when there are media units available to execute write commands for the second write stream, the second write stream is blocked for the lack of buffer space in the cache buffer memory.

At least some aspects of the present disclosure address the above and other deficiencies through timed data transfer between the host system and the memory sub-system. A queuing mechanism is configured to allow commands to be accepted in a memory sub-system without the data to be recorded in the memory sub-system. A queued command can be mapped to a media unit and held in a pending queue per media unit. When the media unit becomes available for executing a write command, the buffer space is allocated for the data of the write command; and the transfer of data for the write command from the host system to the cache buffer memory of the memory sub-system for recording into the media unit is postponed according to the availability of the media unit to accept data. The commands in the queue for the media unit can be executed out of the order in which the commands are received from the host system. The data is transferred via the cache buffer memory just in time for committing, writing, or programming into the media unit. Thus, non-blocking command processing can be performed. Such an arrangement reduces the size requirement of cache buffer memory, and the lifetime of data in the cache buffer memory. For example, the size of cache buffer memory can be reduced to a size that is proportional to the number of media units that are available to support execution of write commands in parallel. The buffer lifetime can be reduced to a time period proportional to the number of data transfers between the host system and the memory sub-system for concurrent execution of the write commands. The significant reduction in cache buffer memory requirements and buffer lifetime reduces the power-fail hold-up requirement. For example, the static random-access memory (SRAM) memory of the controller of the memory sub-system can be used as the cache buffer memory. Dynamic random access memory (DRAM) caching can be eliminated. Such a technique can eliminate the double cost of power-fail-proof of the volatile memory in the computer system, by keeping the more data in the memory that is controlled by the host and that is power-fail-proof using the circuitry in the host system. When such a technique is used, an increased number of host write streams and/or collisions do not increase the requirements for the cache buffer memory and power-fail hold-up circuit in the memory sub-system. Further, such a technique can have the benefit of non-blocking and out of order command processing. Further, transitions among atomic programming modes can be managed based on counting mode transitions that result in single-page data programming and allowing mode transitions that result in two-page data programming after even numbers of single-page transitions, as described in detail further below.

FIG. 1 illustrates an example computing system 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 102), one or more non-volatile memory devices (e.g., memory device 104), or a combination of such.

A memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded multi-media controller (eMMC) drive, a universal flash storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory module (NVDIMM).

The computing system 100 can be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), internet of things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device.

The computing system 100 can include a host system 120 that is coupled to one or more memory sub-systems 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory sub-system 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

The host system 120 can include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and read data from the memory sub-system 110.

The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PC1e) interface, universal serial bus (USB) interface, fibre channel, serial attached SCSI (SAS), a double data rate (DDR) memory bus, small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports double data rate (DDR)), open NAND flash interface (ONFI), double data rate (DDR), low power double data rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. The host system 120 can further utilize an NVM express (NVMe) interface to access components (e.g., memory devices 104) when the memory sub-system 110 is coupled with the host system 120 by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. FIG. 1 illustrates a memory sub-system 110 as an example. In general, the host system 120 can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The processing device 118 of the host system 120 can be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some instances, the controller 116 can be referred to as a memory controller, a memory management unit, and/or an initiator. In one example, the controller 116 controls the communications over a bus coupled between the host system 120 and the memory sub-system 110. In general, the controller 116 can send commands or requests to the memory sub-system 110 for desired access to memory devices 102, 104. The controller 116 can further include interface circuitry to communicate with the memory sub-system 110. The interface circuitry can convert responses received from the memory sub-system 110 into information for the host system 120.

The controller 116 of the host system 120 can communicate with the controller 115 of the memory sub-system 110 to perform operations such as reading data, writing data, or erasing data at the memory devices 102, 104 and other such operations. In some instances, the controller 116 is integrated within the same package of the processing device 118. In other instances, the controller 116 is separate from the package of the processing device 118. The controller 116 and/or the processing device 118 can include hardware such as one or more integrated circuits (ICs) and/or discrete components, a buffer memory, a cache memory, or a combination thereof. The controller 116 and/or the processing device 118 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

The memory devices 102, 104 can include any combination of the different types of non-volatile memory components and/or volatile memory components. The volatile memory devices (e.g., memory device 102) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory components include a negative-AND (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point (“3D cross-point”) memory. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of the memory devices 104 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLCs) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell. In some embodiments, each of the memory devices 104 can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 104 can be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory devices such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 104 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 104 to perform operations such as reading data, writing data, or erasing data at the memory devices 104 and other such operations (e.g., in response to commands scheduled on a command bus by controller 116). The controller 115 can include hardware such as one or more integrated circuits (ICs) and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

The controller 115 can include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory sub-system 110 does not include a controller 115, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 104. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 104. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 104 as well as convert responses associated with the memory devices 104 into information for the host system 120.

The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the controller 115 and decode the address to access the memory devices 104.

In some embodiments, the memory devices 104 include local media controllers 105 that operate in conjunction with the memory sub-system controller 115 to execute operations on one or more memory cells of the memory devices 104. An external controller (e.g., memory sub-system controller 115) can externally manage the memory device 104 (e.g., perform media management operations on the memory device 104). In some embodiments, a memory device 104 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 105) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

The computing system 100 includes a data transfer manager 113 in the memory sub-system 110 that postpones the data transfer for write commands until one or more media units/memory devices are determined to be available for committing, storing, writing, or programming the data into the media units/memory devices. Alternatively, or in combination, the data transfer manager 113 can manage transitions among atomic programming modes to accommodate a constant size of data transfer between a host system and a memory sub-system. In some embodiments, the controller 115 in the memory sub-system 110 includes at least a portion of the data transfer manager 113. In other embodiments, or in combination, the controller 116 and/or the processing device 118 in the host system 120 includes at least a portion of the data transfer manager 113. For example, the controller 115, the controller 116, and/or the processing device 118 can include logic circuitry implementing the data transfer manager 113. For example, the controller 115, or the processing device 118 (processor) of the host system 120, can be configured to execute instructions stored in memory for performing the operations of the data transfer manager 113 described herein. In some embodiments, the data transfer manager 113 is implemented in an integrated circuit chip disposed in the memory sub-system 110. In other embodiments, the data transfer manager 113 is part of an operating system of the host system 120, a device driver, or an application.

The data transfer manager 113 can schedule the data transfer from the host system 120 to the memory sub-system 110 to reduce the amount and time of data buffering in the memory sub-system 110 before the data is committed, stored, written, or programmed into the media units/memory devices 102 to 104. For example, when a media unit (e.g., 102 or 104) is determined to be available (e.g., not busy with other operations) for executing a write command, the data transfer manager 113 initiates the transfer, from the host system 120 to the memory sub-system 110, of the data for the write command. When the media unit (e.g., 102 or 104) is determined to be busy with operations for another command, the data transfer manager 113 postpones the transfer, from the host system 120 to the memory sub-system 110 for the media unit (e.g., 102 or 104), of the data of queued write commands. In general, the data transfer manager 113 is configured to initiate the transfer of data from the host system 120 to the memory sub-system 110 for a subset of the media units 102 to 104 which subset is determined to be available for write operations and postpone the transfer of further data for the remaining subset of the media units 102 to 104 that is busy with other operations. Since the data of the write commands is fetched from the host system 120 just in time for the execution of the write commands, the data transfer manager 113 can reduce and/or minimize the amount and time of data that is being buffered in the memory sub-system 110, in accordance with the bandwidth of the media units/memory devices 102 to 104 to write, store, commit, or program data for storage. Further details with regards to the operations of the data transfer manager 113 are described below.

FIG. 2 shows a data transfer manager 113 configured to control timing of data transfer between a host system 120 and a memory sub-system 110. For example, the data transfer manager 113 of FIG. 2 can be implemented in the computer system 100 of FIG. 1 .

In FIG. 2 , the host system 120 has volatile memory 133 that stores data to be written into the media 203 of the memory sub-system 110.

The host system 120 has a power-fail hold-up circuit 131, which can provide sufficient power to the volatile memory 133 and/or other components of the host system 120 (e.g., processing device(s) 118 illustrated in FIG. 1 ), such that in an event of power failure, data 135 in the volatile memory 133 can be secured. For example, during the power failure event, the power-fail hold-up circuit 131 can power the volatile memory 133 for a period of time that is long enough to allow the data in the volatile memory 133 to be stored into the non-volatile media 203 of the memory sub-system 110, and/or another memory device.

Optionally, the host system 120 can cache the data 135 in non-volatile memory that replaces the volatile memory 133. Thus, the data 135 stored in the non-volatile memory is power-fail-proof; and the power-fail hold-up circuit 131 for the volatile memory 133 can be eliminated. However, the use of non-volatile memory to replace the volatile memory 133 can reduce data access performance and/or increase the cost of the host system 120. In some instances, a combination of volatile memory 133 and non-volatile memory can be used in the host system 120 (e.g., to secure data in a power failure event and/or to improve data access performance).

In FIG. 2 , the data transfer manager 113 of the memory sub-system 110 can maintain at least one command queue 143 for commands received from the controller 116 of the host system 120. The commands in the queue 143 can be stored in the local memory 119 of the controller (e.g., 115 illustrated in FIG. 1 ) of the memory sub-system 110. Write commands from the host system 120 can be accepted into the queue 143 without the data to be written into the media 203. The queuing of the commands allows out of order execution of the commands in the memory sub-system 110 for performance optimization in some situations.

In FIG. 2 , the local memory 119 has a power-fail hold-up circuit 141 that can be used to protect the content (e.g., 145 and 143) in the local memory 119 during a power failure event. During the power failure event, the power-fail hold-up circuit 141 can power the local memory 119 for a period of time that is long enough to allow the content to be is stored into non-volatile memory (e.g., media 203).

Optionally, the local memory 119 can be implemented using a non-volatile memory to remove the need for the power-fail hold-up circuit 141, or using a combination of non-volatile memory to reduce the requirement for the power-fail hold-up circuit 141.

In FIG. 2 , the data transfer manager 113 is configured to time/schedule the data transfer between the host system 120 and the memory sub-system 110 and thus reduce the size requirement for the local memory 119 and/or the capacity requirement for the power-fail hold-up circuit 141.

For example, the data transfer manager 113 does not automatically accept and/or transfer data of all write commands queued in the command queue 143. To reduce the amount of data 145 being buffered in the local memory 119, the data transfer manager 113 postpones the transfer of data of a write command and initiates the transfer when one of the media units (e.g., 109A or 109N, such as memory devices 102 and/or 104 illustrated in FIG. 1 ) is determined to be ready for execution of the write command.

Thus, for each of the media units 109A to 109N, the local memory 119 can buffer the data of some write commands but not the data of other write commands. In some implementations, the local memory 119 is configured to buffer data for no more than a predetermined number of commands (e.g., one command per media unit, or two, or another number). However, the command queue 143 can buffer more write commands for each of the media units 109A to 109N (e.g., to enable out of order command execution) than the local memory 119 can buffer the data of write commands for the respective media unit (e.g., 109A or 109N).

The technique of buffering the commands with reduced buffering of the data of the commands can be particularly advantageous when the size ratio/ratios between the commands and their data is/are large.

Optionally, the data transfer manager 113 can configure a queue (e.g., 143) for each of the media units 109A to 109N. Alternatively, the data transfer manager 113 can configure a combined command queue (e.g., 143) for the media units 109A to 109N and dynamically assign write commands to the media units 109A to 109N when the media units 109A to 109N become available for execution of write commands. For example, when a write command is ready to be executed in an available media unit (e.g., 109A or 109N), a portion of the media layout for mapping the logical addresses identified in the write command can be dynamically generated to map the logical addresses to memory locations in the currently available media unit (e.g., 109A or 109N). Thus, the write command can be executed in the available media unit (e.g., 109A or 109N).

FIG. 3 shows an example of a memory sub-system having timed data transfer. For example, the memory sub-system of FIG. 3 can be implemented in the memory sub-system 110 of FIG. 1 using a data transfer manager 113 of FIG. 2 . However, the techniques of FIG. 1 and FIG. 2 are not limited to the implementation of the memory sub-system illustrated in FIG. 3 . For example, the techniques can be implemented in a plain block device, a device that supports namespaces, or a device that supports zoned names spaces (e.g., a memory sub-system illustrated in FIG. 3 ). Thus, the disclosure presented herein is not limited to the example of FIG. 3 .

In FIG. 3 , a namespace 201 is configured on the media storage capacity of the memory sub-system 110. The namespace 201 provides a logical block addressing space that can be used by the host system 120 to specify memory locations for read or write operations. The namespace 201 can be allocated on a portion of the media storage capacity of the memory sub-system 110, or the entire media storage capacity of the memory sub-system 110. In some instances, multiple namespaces can be allocated on separate, non-overlapping portions of the media storage capacity of the memory sub-system 110.

In FIG. 3 , the namespace 201 is configured with a plurality of zones 211, 213, . . . , 219. Each zone (e.g., 211) in the namespace allows random read access to local block addressing (LBA) addresses in the zone (e.g., 211) and sequential write access to LBA addresses in the zone (e.g., 211), but does not allow random write access to random LBA addresses in the zone (211). Thus, writing data into a zone (e.g., 211) is performed in a predetermined, sequential order in the LBA address space of the namespace 201.

When a zone (e.g., 211) in the namespace 201 is configured, it is possible to predetermine the media layout for the zone (e.g., 211) (e.g., for simplicity). The LBA addresses in the zone (e.g., 211) can be pre-mapped to the media 203 of the memory sub-system 110. However, such a predetermined media layout can cause media access collisions when there are multiple parallel write streams, as discussed above. Randomize the mapping from LBA addresses in the zone (e.g., 211) to memory locations in the media 203 can reduce collisions but cannot eliminate collisions.

Preferably, a dynamic data placer 153 is configured in the memory sub-system 110 to create portions of the media layout 130 at the time of the scheduling of write commands for execution such that media access collisions are completely eliminated. In some implementations, the dynamic data placer 153 can be part of the data transfer manager 113.

For example, the media 203 of the memory sub-system 110 can have multiple integrated circuit dies 205, . . . , 207. Each of the integrated circuit dies (e.g., 205) can have multiple planes 221, . . . , 223 of memory units (e.g., NAND memory cells). Each of the planes (e.g., 221) can have multiple blocks 231, . . . , 233 of memory units (e.g., NAND memory cells). Each of the blocks (e.g., 231) can have multiple pages 241, . . . , 243 of memory units (e.g., NAND memory cells). The memory units in each page (e.g., 241) is configured to be programmed to store/write/commit data together in an atomic operation; and the memory units in each block (e.g., 231) is configured to be erased data together in an atomic operation.

When a write command (e.g., 123A) for storing data in one zone (e.g., 211) and another write command (e.g., 123N) for storing data in another zone (e.g., 213) are scheduled for parallel execution as a result of two integrated circuit dies (e.g., 205 and 207) are available for concurrent operations for the write commands (e.g., 123A and 123N), the dynamic data placer 153 maps the LBA addresses of the write commands into pages located in the different dies (e.g., 205 and 207). Thus, media access collisions can be avoided.

Further, when the two integrated circuit dies (e.g., 205 and 207) are determined to be available for the execution of the write commands (e.g., 123A and 123N), the data transfer manager 113 initiates the transfer of the data 145 for the write commands (e.g., 123A and 123N) from the memory 133 of the host system 120 to the local memory 119 of the memory sub-system 110. Thus, most of the data 135 of the write commands in the queue 143 can be stored in the host memory 133, while the corresponding write commands themselves are accepted in the command queue 143 in the memory sub-system 110. The data 145 is for the write commands (e.g., 123A and 123N) that are ready to be executed for storing data into the memory cells in the integrated circuit dies (e.g., 205 and 207) that are available to service the write commands (e.g., 123A and 123N). Since only the data 145 is transferred just in time for the available integrated circuit dies (e.g., 205 and 207), the lifetime of the data 145 being buffered in the local memory 119 is reduced and/or minimized. Further, the amount of the data 145 buffered in the local memory 119 can be reduced and/or minimized. The reduction of the lifetime and amount of the data 145 of write commands can reduce the requirement for securing the content of the local memory 119 in a power failure event.

FIG. 4 illustrates an example of data structures configured to support data transfer between a host system and a memory sub-system. For example, the media layout 130 of FIG. 3 can be implemented using the data structures of FIG. 4 .

In FIG. 4 , a zone map 301 is configured to provide media layout information for a zone (e.g., 211) in a namespace (e.g., 201). The zone map 301 can have multiple entries. Each entry in the zone map 301 identifies information about a zone (e.g., 211), such as a starting LBA address 311 of the zone (e.g., 211), a block set identifier 313 of the zone (e.g., 211), a cursor value 315 of the zone (e.g., 211), a state 317 of the zone (e.g., 211), etc.

The host system 120 writes data in the zone (e.g., 211) starting at the zone starting LBA address 311. The host system 120 writes data in the zone (e.g., 211) sequentially in the LBA space. After an amount of data has been written into the zone (e.g., 211), the current starting LBA address for writing subsequent data is identified by the cursor value 315. Each write command for the zone moves the cursor value 315 to a new starting LBA address for the next write command for the zone. The state 317 can have a value indicating that the zone (e.g., 211) is empty, full, implicitly open, explicitly open, closed, etc.

In FIG. 4 , a logical to physical block map 303 is configured to facilitate the translation of LBA addresses (e.g., 331) into physical addresses in the media (e.g., 203).

The logical to physical block map 303 can have multiple entries. An LBA address (e.g., 331) can be used as, or converted into, an index for an entry in the logical to physical block map 303. The index can be used to look up an entry for the LBA address (e.g., 331). Each entry in the logical to physical block map 303 identifies, for an LBA address (e.g., 331), the physical address of a block of memory in the media (e.g., 203). For example, the physical address of the block of memory in the media (e.g., 203) can include a die identifier 333, a block identifier 335, a page map entry identifier 337, etc.

A die identifier 333 identifies a specific integrated circuit die (e.g., 205 or 207) in the media 203 of the memory sub-system 110.

A block identifier 335 identifies a specific block of memory (e.g., NAND flash memory) within the integrated circuit die (e.g., 205 or 207) that is identified using the die identifier 333.

A page map entry identifier 337 identifies an entry in a page map 305.

The page map 305 can have multiple entries. Each entry in the page map 305 can include a page identifier 351 that identifies a page of memory cells within a block of memory cells (e.g., NAND memory cells). For example, the page identifier 351 can include a word line number for the page and a sub block number for the page in the block of NAND memory cells. Further, the entry for the page can include a programming mode 353 of the page. For example, the page can be programmed in an SLC mode, an MLC mode, a TLC mode, or a QLC mode. When configured in the SLC mode, each memory cell in the page is to store one bit of data. When configured in the MLC mode, each memory cell in the page is to store two bits of data. When configured in the TLC mode, each memory cell in the page is to store three bits of data. When configured in the QLC mode, each memory cell in the page is to store four bits of data. Different pages in an integrated circuit die (e.g., 205 or 207) can have different modes for data programming.

In FIG. 4 , the block set table 307 stores data controlling aspects of the dynamic media layout for a zone (e.g., 211).

The block set table 307 can have multiple entries. Each entry in the block set table 307 identifies a number/count 371 of integrated circuit dies (e.g., 205 and 207) in which data of the zone (e.g., 211) is stored. For each of the integrated circuit dies (e.g., 205 and 207) used for the zone (e.g., 211), the entry of the block set table 307 has a die identifier 373, a block identifier 375, a page map entry identifier 377, etc.

The die identifier 373 identifies a specific integrated circuit die (e.g., 205 or 207) in the media 203 of the memory sub-system 110, on which die (e.g., 205 or 207) subsequent data of the zone (e.g., 211) can be stored.

The block identifier 375 identifies a specific block (e.g., 231 or 233) of memory (e.g., NAND flash memory) within the integrated circuit die (e.g., 205 or 207) that is identified using the die identifier 373, in which block (e.g., 231 or 233) the subsequent data of the zone (e.g., 211) can be stored.

The page map entry identifier 337 identifies an entry in the page map 305, which identifies a page (e.g., 241 or 241) that can be used to store the subsequent data of the zone (e.g., 211).

FIG. 5 shows a method of timed data transfer. The method of FIG. 5 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method of FIG. 5 is performed at least in part by the data transfer manager 113 of FIG. 1, 2 , or 3. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At block 401, a memory sub-system 110 receives multiple streams of write commands from a host system 120. For example, each respective stream in the multiple streams is configured to write data sequentially in a logical address space in one embodiment; and in another embodiment, a stream in the multiple streams is configured to write data pseudo-sequentially, or randomly in a logical address space in one embodiment. Each write stream includes a set of commands that are tagged to write, trim, overwrite a set of data together as a group. In the group, the data can be written in a logical space sequentially, randomly, or pseudo-sequentially. Preferably, the data in the group is written into an erase block set, where memory cells in the erase block set store data for the stream but not data from other streams. The erase block set can be erased to remove the data of the stream without erasing the data of other streams.

For example, each of write streams is permitted to sequentially write at LBA addresses in a zone (e.g., 211) in a namespace (e.g., 201) allocated on a media 203 of the memory sub-system 110, but prohibited from writing data out of sequence in the LBA address space.

At block 403, a data transfer manager 113 of the memory sub-system 110 identifies multiple media units (e.g., 109A to 109N) in the memory sub-system 110 that are available to write data concurrently.

At block 405, the data transfer manager 113 selects first commands from the multiple streams for concurrent execution in the multiple media units that are available to write data.

At block 407, the data transfer manager 113 initiates, in response to the first commands being selected for concurrent execution in the multiple media units, communication of first data of the first commands from the host system 120 to a local buffer memory 119 of the memory sub-system 110. For example, the transferring of the first data is postponed until the multiple media units are available to perform write operations for storing the first data. The postponed transfer reduces the time of the first data being buffered. In response to the multiple media units being available to perform write operations, a buffer space in the local buffer memory 119 is allocated for the first data for the buffering of the first data communicated from the host system 120 to the memory sub-system 110.

At block 409, the memory sub-system 110 executes the first commands concurrently by storing data into the multiple memory units. For example, as soon as the first data has been transferred from the local buffer memory 119 to the multiple media units, the buffer space allocated for the first data can be released from buffering the first data. In some instances, the buffer space can be released before the multiple media units completes programming/writing the first data.

For example, at the time of scheduling the first commands for execution, execution second commands can be in progress in a subset of memory units of the media 203 of the memory sub-system 110. Thus, the subset of memory units used for the execution of the second commands are not available for the first commands. After the first commands are scheduled for a subset of memory units of the media 203 of the memory sub-system 110, the data transfer manager 113 initiates the transfer of the data to be written via the first commands from the host system 120 to the memory sub-system 110. The just-in-time transfer of the data of the first commands reduces the amount and time of data being buffered in the local memory 119 of the memory sub-system 110 and thus reduces the capacity requirement of the local memory 119 and the capacity requirement of the power-fail hold-up circuit 141 configured for the local memory 119. The first commands can be executed in the multiple media units concurrently and/or concurrently with the progress of the execution of the second commands in remaining media units of the memory sub-system 110.

For example, the memory sub-system 110 is configured to buffer, in the local buffer memory 119, no more than a predetermined number of units of data. The predetermined number corresponds to the number of media units 109A to 109N in the memory sub-system 110 that are capable of operating independent from each other in writing data. Each unit of data is no more than a maximum amount of data to be written in a media unit (e.g., 109A or 109N) in response to a single write command. Thus, the buffer capacity of the local memory 119 does not limit the number of write streams the host system 120 can send to the memory sub-system 110. The reduced amount and time of data being buffered in the local memory 133 can reduce the requirement for the corresponding power-fail hold-up circuit 141 of the memory sub-system 110.

The memory sub-system 110 can accept and queue write commands in one or more queues 143 in the local memory 119. The number of queued write commands can be significantly more than the predetermined number of units of data that can be buffered in the local memory 119. Since the performance of the memory sub-system 110 is limited by the bandwidth of the media units 109A to 109N to commit, write, store, or program data concurrently in execution of concurrent write commands, the limited buffer capacity of the local memory 119 for the data of write commands does not impact the performance of the memory sub-system 110.

When more commands are queued than what can be executed concurrently, the memory sub-system 110 can selectively execution certain commands out of their order in arriving in the memory sub-system 110.

The reduced buffer memory requirement allows the local memory 119 to be configured as static random access memory (SRAM) of the controller 115 and thus eliminate the need for DRAM in buffering data to be written in the media 203 of the memory sub-system 110. For example, a capacity of the static random access memory (SRAM) to buffer data of write commands can be less than the capacity required to buffer all of write commands queued in the memory sub-system.

Optionally, each respective media unit (e.g., 109A or 109N) has a command queue for write commands that are configured to write data into the respective media unit (e.g., 109A or 109N). The command queue can store multiple write commands; and the local memory 119 can be configured to limit its buffer memory for the data of the write commands. For example, the buffer memory can be limited to the capacity of a small portion of the commands in the queue. For example, the buffer memory can be limited to the size of the data that can be programmed/written/stored/committed into the respective media unit (e.g., 109A or 109N) in response to a single write command (or a predetermined number write commands that is smaller than a total number of write commands that can be queued for the respective media unit).

Optionally, the portion of the media layout 130 for the logical addresses used in the first commands is determined dynamically in response to the determination that the first commands can be executed concurrently in the available media units.

For example, after the identification of the multiple memory units (e.g., integrated circuit dies) that are available for the execution of next commands, the data transfer manager 113 can identify, from the block set table 307, the physical addresses that can be used to store data of the next commands. The physical addresses can be used to update the corresponding entries in the logical to physical block map 303 for the LBA addresses used in the next commands.

For example, when an integrated circuit die (e.g., 205) is free to write data, the data transfer manager 113 can determine a command of a zone that can be written/programmed into the memory cells in the integrated circuit die (e.g., 205). From the block set table 307, the data transfer manager 113 and/or the dynamic data placer 153 can locate an entry for the zone (e.g., 205), locate the block identifier 375 and the page map entry identifier 377 associated with the identifier 373 of the integrated circuit die (e.g., 205), and use the die identifier 373, the block identifier 375, and the page map entry identifier 377 to update the corresponding fields of the entry in the logical to physical block map 303 for the LBA address 331 used in the command of the zone (e.g., 211). Thus, the command of the zone (e.g., 211) can be executed without media access collision for the LBA address 331.

In a media unit (e.g., 109A to 109N or 205 to 207), memory cells (e.g., of a NAND type) can be organized in blocks (e.g., 231 to 233) where memory cells in each block are to be erased together in an atomic operation. A block of memory cells can be divided into sub-blocks and pages. A page of memory cells is a smallest unit of memory cells that are programmed together in an atomic operation. Pages for a given word line within a sub-block and across sub-blocks are generally not programmed in order. Page programming order within a block can jump across word lines, sub-blocks and pages for the optimization of signal to noise ratio (SNR) across word lines and sub-blocks. Thus, the page programming order within a block can be irregular and have a pattern that is complex.

Due to multi-pass programming and irregular page map, atomic programming granularity is not fixed and is variable. When a host system issues write commands with a fixed/constant input/output (I/O) size, the host I/O size does not always match the programming granularity of the media. The mismatch can increase the requirements for the controller memory and for power backup, which can lead to increased cost.

In at least some embodiments disclosed herein, the page map can still be irregular to accommodate for varying SNR ratios across word lines within a sub-block and across sub-blocks in a block. However, the page map is scheduled according to a restriction such that a fixed host I/O size can be matched to a fixed atomic programming size. The restriction is based on a count of transitions of programming modes of a particular type, as further discussed below.

FIG. 6 illustrates of sizes of data to be programmed in atomic programming operations responsive to transitions of programming modes.

A multi-pass programming technique can be implemented using multiple atomic programming operations. Each of the atomic programming operations can transit from one memory cell programming mode to another.

For example, when a multi-pass programming technique is applied to a set of pages of memory cells for TLC programming, the multi-pass TLC programming can be implemented via a number of transitions of atomic programming modes. For example, the multi-pass TLC programming can initial on a set of fresh pages that have not yet been programmed to store data (e.g., after an erasure operation). The new multi-pass TLC programming can transit from no programming on the set of fresh pages to atomic SLC programming of a page of memory cells to store one page of data of a predetermined size. Alternatively, the new multi-pass TLC programming can transit from no programming to atomic MLC programming of two pages of data, where each page has the predetermined size. Subsequently, the multi-pass TLC programming can optionally transit from atomic SLC programming to atomic MLC programming of one page of data of the predetermined size as a result of the transition. Optionally, the multi-pass TLC programming can continue by transiting from atomic SLC programming to atomic TLC programming of, as a result of the transition, two pages of data, where each page has the predetermined size. Alternatively, the multi-pass TLC programming can transit from atomic MLC programming to atomic TLC programming of one page of data of the predetermined size, as a result of the transition.

Similarly, when a multi-pass programming technique is applied to a set of pages of memory cells for QLC programming, the multi-pass QLC programming can be implemented via a number of transitions of atomic programming modes. The multi-pass QLC programming can have the transitions as in multi-pass TLC programming. Further, the multi-pass QLC programming can optionally transit from atomic MLC programming to atomic QLC programming of two pages of data, each page having the predetermined size. Alternatively, the multi-pass QLC programming can optionally transit from atomic TLC programming to atomic QLC programming of one page of data of the predetermined size, as a result of the transition.

The page counts for the transition options illustrated in FIG. 6 can be used to manage programming mode transitions in a memory sub-system 110, as further discussed below in connection with FIG. 7 . For example, transition types that have atomic programming size of one page can be interleaved with transition types that have atomic programming size of two pages; and an even number of transition types that have atomic programming size of one page is required to occur in sequence before one or more subsequent transitions that have atomic programming size of two pages are allowed. When an irregular page map does not follow this pattern of transitions, a fixed host input/output size cannot be always mapped to the next atomic programming granularity.

For example, atomic programming granularity sequence of “one page, two pages, etc.” does not follow the pattern of having a two-page transition after an even number of single-page transitions. As a result, there can be difficulties in mapping to a fixed host input/output size (e.g., one page or two pages) to the sequence. For example, the host size is fixed at one page. After the first programming at one page, the next host input/out of one page cannot be processed until another host input/out is received and mapped to the same die and block to make the atomic programming of two pages. In another example, the host size is fixed at two pages. The first half of the host input/output of two pages can be programmed using the atomic programming of one page. However, the second half of the host input/output of two pages cannot be programmed until another host input/out is received and mapped to the same die and block to make the atomic programming of two pages. The waiting for the next input/out mapped to the same die and block can increase buffer memory usage and the lifetime of data being buffered in the memory, especially when there are multiple outstanding commands that do not match the atomic granularity. The increased buffer memory usage and the lifetime of data being buffered can increase the requirements for controller memory and power fail-safe backup capacity.

However, when the atomic programming granularity sequence of “one page, one page, two pages, etc.” is used to have the pattern of an even number of single-page transitions following a two-page transition, a fixed host input/output size can be matched with the atomic programming granularity in the sequence. For example, when the host size is fixed at two pages. Thus, the first half of the host input/output of two pages can be programmed using the first atomic programming of one page; and the second half can be programmed using the second atomic programming of one page. The next host input/output of two pages can be programmed using the following programming of two pages.

If the zone/stream size is a 4 (multi-plane) block, then due to irregular page map, a mix of 2-plane and 4-plane programming has to be used, instead of always using 4-plane programming, so as to match a fixed host IO size (example 4 pages). By not using 4-plane programming all the time, but using a mix of 2-plane and 4-plane programming causes performance loss and increased power consumption.

Thus, it is advantageous to implement a page map sequence where 1) transition types that have atomic programming size of 1 page are interleaved with transition types that have atomic programming size of 2 pages; and 2) an even number of transition types that have atomic programming size of 1 page must occur in sequence before a sequence of transitions that have atomic programming size of 2 pages occurs. This pattern can repeat any number of times in the page map sequence.

FIG. 7 shows a method to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The method of FIG. 7 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method of FIG. 5 is performed at least in part by the data transfer manager 113 and/or the dynamic data placer 153 of FIG. 1, 2 , or 3. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At block 421, the data transfer manager 113 and/or the dynamic data placer 153 starts counting single-page transitions of atomic programming modes performed within a memory sub-system (e.g., 110). Each single-page transition results in atomic programming of a single-page of data of a predetermined size.

At block 423, the data transfer manager 113 and/or the dynamic data placer 153 determines whether an odd or even number of the transitions have been counted.

For example, a one-bit counter can be used to count the single-page transitions of atomic programming modes. The one-bit counter can be initially set to have a value of zero. When a single-page transition occurs, one can be added (e.g., via a logic AND operation) to the one-bit counter to update its content.

If it is determined that at block 425 an odd number of single-page transitions of atomic programming modes have been counted, the data transfer manager 113 and/or the dynamic data placer 153 prohibits at block 427 a two-page transition of atomic programming modes. Each two-page transition results in atomic programming of two pages of data, where each page has the predetermined size.

If it is determined that at block 425 an even number of single-page transitions of atomic programming modes has occurred, the data transfer manager 113 and/or the dynamic data placer 153 allows at block 429 one or more two-pages transitions of atomic programming modes. Each two-page transition results in atomic programming of two pages data with each page having the predetermined size.

For example, the one-bit counter has a value of one, any two-page transitions can be blocked temporally, until the one-bit counter has a value of zero.

At block 431, the data transfer manager 113 and/or the dynamic data placer 153 selects a transition of programming modes in accordance with the restriction/permission as determined in blocks 427 and 429.

At block 433, the data transfer manager 113 and/or the dynamic data placer 153 updates counting of transitions of programming modes.

The operations in the blocks 423 to 433 can be repeated for the programming of pages in the block.

For example, multi-pass programming operations can be performed to store data. Each multi-pass programming operation can be operated on a set of pages via multiple atomic programming operations in the memory sub-system 110. Each multi-pass programming operation can store at least one page of memory cells in a triple level cell (TLC) mode or a quad-level cell (QLC) mode. The atomic programming operations can transit from a first mode to a second mode, where the first and second modes are different ones of: no programming; programming to store one bit in each memory cell; programming to store two bits in each memory cell; programming to store three bits in each memory cell; and programming to store four bits in each memory cell.

A single-page transition can be a transition from no programming to a single level cell (SLC) mode, from the single level cell (SLC) mode to a multi-level cell (MLC) mode, from the multi-level cell (MLC) mode to a triple level cell (TLC) mode, or from the triple level cell (TLC) mode to a quad-level cell (QLC) mode.

A two-page transition can be from the single level cell (SLC) mode to the triple level cell (TLC) mode, from the multi-level cell (MLC) mode to the quad-level cell (QLC) mode, or from no programming to the multi-level cell (MLC) mode.

The memory sub-system 110 can receive multiple streams of write commands from a host system 120 and perform multi-pass programming data to store the data in multiple planes in one or more media units (e.g., dies 205 to 207). The memory sub-system 110 can select a next transition of atomic programming modes based on the determining of whether or not to allow any two-page transition of atomic programming modes and to match the size of atomic programming mode resulting from the next transition to a size of a write command from the host system.

In some implementations, a communication channel between the processing device 118 and a memory sub-system 110 includes a computer network, such as a local area network, a wireless local area network, a wireless personal area network, a cellular communications network, a broadband high-speed always-connected wireless communication connection (e.g., a current or future generation of mobile network link); and the processing device 118 and the memory sub-system can be configured to communicate with each other using data storage management and usage commands similar to those in NVMe protocol.

A memory sub-system 110 in general can have non-volatile storage media. Examples of non-volatile storage media include memory cells formed in an integrated circuit and magnetic material coated on rigid disks. Non-volatile storage media can maintain the data/information stored therein without consuming power. Memory cells can be implemented using various memory/storage technologies, such as NAND logic gate, NOR logic gate, phase-change memory (PCM), magnetic random access memory (MRAM), resistive random-access memory, cross point storage and memory devices (e.g., 3D XPoint memory). A cross point memory device uses transistor-less memory elements, each of which has a memory cell and a selector that are stacked together as a column. Memory element columns are connected via two perpendicular layers of wires, where one layer is above the memory element columns and the other layer below the memory element columns. Each memory element can be individually selected at a cross point of one wire on each of the two layers. Cross point memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

The controller (e.g., 115) of a memory sub-system (e.g., 110) can run firmware to perform operations responsive to the communications from the processing device 118. Firmware in general is a type of computer program that provides control, monitoring and data manipulation of engineered computing devices.

Some embodiments involving the operation of the controller 115 can be implemented using computer instructions executed by the controller 115, such as the firmware of the controller 115. In some instances, hardware circuits can be used to implement at least some of the functions. The firmware can be initially stored in the non-volatile storage media, or another non-volatile device, and loaded into the volatile DRAM and/or the in-processor cache memory for execution by the controller 115.

A non-transitory computer storage medium can be used to store instructions of the firmware of a memory sub-system (e.g., 110). When the instructions are executed by the controller 115 and/or the processing device 117, the instructions cause the controller 115 and/or the processing device 117 to perform a method discussed above.

FIG. 8 illustrates an example machine of a computer system 500 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 500 can correspond to a host system (e.g., the host system 120 of FIG. 1 ) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1 ) or can be used to perform the operations of a data transfer manager 113 (e.g., to execute instructions to perform operations corresponding to the data transfer manager 113 described with reference to FIGS. 1-7 ). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530 (which can include multiple buses).

Processing device 502 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 can further include a network interface device 508 to communicate over the network 520.

The data storage system 518 can include a machine-readable storage medium 524 (also known as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 can also reside, completely or at least partially, within the main memory 504 and/or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, data storage system 518, and/or main memory 504 can correspond to the memory sub-system 110 of FIG. 1 .

In one embodiment, the instructions 526 include instructions to implement functionality corresponding to a data transfer manager 113 (e.g., the data transfer manager 113 described with reference to FIGS. 1-8 ). While the machine-readable storage medium 524 is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

In this description, various functions and operations are described as being performed by or caused by computer instructions to simplify description. However, those skilled in the art will recognize what is meant by such expressions is that the functions result from execution of the computer instructions by one or more controllers or processors, such as a microprocessor. Alternatively, or in combination, the functions and operations can be implemented using special purpose circuitry, with or without software instructions, such as using application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). Embodiments can be implemented using hardwired circuitry without software instructions, or in combination with software instructions. Thus, the techniques are limited neither to any specific combination of hardware circuitry and software, nor to any particular source for the instructions executed by the data processing system.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. 

What is claimed is:
 1. A device, comprising: an interface configured to communicate with a host system; a plurality of media units; and a logic circuit configured to manage programming of pages in the media units to accommodate a predetermined characteristics of data transfer through the interface.
 2. The device of claim 1, wherein the predetermined characteristics is associated with a rate of data transfer between the device and host system over the interface.
 3. The device of claim 2, wherein the logic circuit is configured to manage the programming of the pages in the media units to accommodate the rate to be constant.
 4. The device of claim 3, wherein the logic circuit is configured to perform multi-pass programming of pages in the media units.
 5. The device of claim 4, wherein the multi-pass programming includes a plurality of atomic programming operations; and the logic circuit is configured to manage transitions between modes of programming a memory cell in the atomic programming operations.
 6. The device of claim 4, wherein the multi-pass programming includes: a first atomic programming of a single data page of a predetermined size in the media units; and a second atomic programming of two data pages each having the predetermined size in the media units.
 7. The device of claim 6, wherein the logic circuit is configured to determine a count of first transitions in modes of programming a memory cell in the first atomic programming and manage, based on the count, second transitions in modes of programming a memory cell in the second atomic programming.
 8. The device of claim 7, wherein the first transitions are transitions from a first mode to a second mode; and the first mode and the second mode are different ones of: no programming; programming to store one bit in each memory cell; programming to store two bits in each memory cell; programming to store three bits in each memory cell; and programming to store four bits in each memory cell.
 9. A method, comprising: communicating, by a device having a plurality of media units, with a host system to write data from the host system into the media units; and managing, by the device, programming of pages in the media units to accommodate a predetermined characteristics of data transfer between the device and the host system.
 10. The method of claim 9, wherein the predetermined characteristics is associated with a rate of data transfer between the device and host system.
 11. The method of claim 10, further comprising: accommodating, based on the managing, the rate to be constant.
 12. The method of claim 11, wherein the programming of the pages in the media units includes multi-pass programming of the pages in the media units.
 13. The method of claim 12, wherein the multi-pass programming includes a plurality of atomic programming operations; and the managing includes managing transitions between modes of programming a memory cell in the atomic programming operations.
 14. The method of claim 13, wherein the multi-pass programming includes: a first atomic programming of a single data page of a predetermined size in the media units; and a second atomic programming of two data pages each having the predetermined size in the media units.
 15. The method of claim 14, wherein the managing of the transitions includes: determining a count of first transitions in modes of programming a memory cell in the first atomic programming; and managing, based on the count, second transitions in modes of programming a memory cell in the second atomic programming.
 16. The method of claim 15, wherein the first transitions are transitions from a first mode to a second mode; and the first mode and the second mode are different ones of: no programming; programming to store one bit in each memory cell; programming to store two bits in each memory cell; programming to store three bits in each memory cell; and programming to store four bits in each memory cell.
 17. A computing system, comprising: a device having a plurality of media units; and a host system connected to the device to write data into the device; wherein the device is configured to manage programming of pages in the media units to accommodate a constant rate of data transfer between the device and the host system in writing the data into the device.
 18. The computing system of claim 17, wherein the device configured to perform multi-pass programming of pages in the media units via a plurality of atomic programming operations, including a first atomic programming of a single data page of a predetermined size in the media units and a second atomic programming of two data pages each having the predetermined size in the media units; and wherein the device is further configured to manage transitions between modes of programming a memory cell in the atomic programming operations.
 19. The computing system of claim 18, wherein the device is configured to determine a count of first transitions in modes of programming a memory cell in the first atomic programming and manage, based on the count, second transitions in modes of programming a memory cell in the second atomic programming.
 20. The computing system of claim 19, wherein the first transitions are transitions from a first mode to a second mode; and the first mode and the second mode are different ones of: no programming; programming to store one bit in each memory cell; programming to store two bits in each memory cell; programming to store three bits in each memory cell; and programming to store four bits in each memory cell. 